In the AI Frenzy Forum held today, Yu Chao, vice president of research at TrendForce, pointed out that the global IC design industry has officially entered the long-cycle growth stage driven by AI. AI is redefining chip architecture, memory integration and high-speed interconnection, and promoting cloud computing, edge inference and self-developed chips to become the three key forces in the market, indicating that the next five years will be the most dramatic restructuring period in the IC design industry.
TrendForce estimates that the annual compound growth rate of the global IC design market from 2024 to 2029 is expected to approach double digits; among which, the overall global IC design and semiconductor market size will reach US$782 billion in 4Q 2025, becoming an important inflection point for the overall increase in demand driven by AI.
Chu Yuchao pointed out that the growth momentum in recent years has obviously shifted from a structure dominated by consumer electronics in the past to AI-related applications such as cloud computing, edge inference and memory integration. The rapid increase in computing density of AI servers has driven the continuous increase in the production volume of GPUs, AI accelerators and ASICs dedicated to large language models, allowing advanced processes below 5 nanometers to maintain strong expansion. At the same time, large data centers no longer only pursue peak computing power, but require higher bandwidth, larger caches and better energy efficiency, pushing IC architecture into a new stage of "equal emphasis on performance and energy efficiency".
Cloud × edge dual-axis propulsionHe emphasized that the growth of AI is not only happening in the cloud, but is also penetrating into various Edge devices. From mobile phones and laptops to automotive SoCs and industrial control chips, the introduction of lightweight inference engines is accelerating, causing the market to gradually form a "dual-axis growth pattern" of cloud training and edge inference, and become an important source of support for IC design demand after 2025.
In terms of architecture, memory integration is still one of the cores of this round of AI transformation. Chu Yuchao said that the bandwidth and stacking limitations of HBM require AI chips to adopt a tighter "logic-memory co-design" approach, placing higher requirements on controllers, memory interfaces, cache levels and thermal management than ever before.
Interconnection, packaging and the rise of self-developed chipsIn addition to memory, high-speed interconnection and packaging technology have also become another force redefining chip architecture. As the scale of AI models continues to expand and data throughput increases rapidly, traditional telecommunications signals are approaching physical limits, causing CPO (Co-Packaged Optics) to gradually move from conceptual technology to actual deployment in data centers. Chu Yuchao pointed out that bringing the optical interface close to the ASIC can not only improve data transmission efficiency, but also significantly reduce heat accumulation in the package. In the future, it may reshape the way the chip provides external I/O, expanding the scope of competition in IC design from logic and memory to interconnection and packaging collaboration.
Another force that is accelerating market restructuring is that global cloud service providers (CSPs) are fully investing in self-developed chips. Google, AWS, Microsoft, Meta and even OpenAI are all accelerating the launch of their own training or inference chips to reduce dependence on GPUs, improve energy consumption and control long-term costs. Chu Yuchao believes that the penetration rate of self-developed chips may double in the next five years, rewriting the HPC chip supply chain and driving the rapid expansion of demand for IP, ASIC design services and advanced packaging.
As energy efficiency requirements increase, computing costs rise, and supply chain reorganization accelerates, IC design technology and business models will face profound changes.